The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices, such as a system on a chip (SoC) device having a microprocessor, are electrically coupled to static random access memory (SRAM) devices for the storage of digital data, including SRAM register files having more than one port for reading and/or writing data. In a conventional six-transistor (6T) SRAM cell, an issue called half select disturb can affect both read and write operations. Half select disturb affects unselected column memory cells in the same row as a selected column memory cell which degrades SRAM static noise margin and data stability. One approach to addressing half select disturb in a read operation is to use an 8T-SRAM cell which isolates the read port from the bit-line (BL). However, the 8T-SRAM cell still suffers from the half select disturb issue when there is an unselected column cell in the same row as a selected column cell during a write operation. Furthermore, if a simultaneous read operation were to occur to a row being written, a leakage current in the read bit line (BL) can also occur, potentially causing the stored data to be misread. It would be beneficial to mitigate or resolve problems associated with half select disturb.